Computer Systems and Architecture

Computer systems are built on a layered architecture that enables efficient data processing, storage, and control.
This section explores the fundamentals of computer architecture, focusing on system organization, CPU design, instruction cycles, and performance metrics.

The Von Neumann Model

The Von Neumann architecture, proposed by John von Neumann in 1945, describes a digital computing system in which data and instructions share the same memory.

Characteristics

• Single memory space for data and program instructions.
• Sequential execution of instructions (Fetch → Decode → Execute).
• Control Unit (CU) manages instruction flow.
• Arithmetic Logic Unit (ALU) performs computations.

graph TD
  subgraph "Von Neumann Architecture"
    CPU[CPU]
    CU[Control Unit]
    ALU[Arithmetic Logic Unit]
    MEM[Main Memory]
    I_O[I/O Devices]
    BUS[System Bus]
  end

  CPU --> MEM
  MEM --> CPU
  CPU --> I_O
  I_O --> CPU
  CPU --> BUS
  BUS --> MEM

Harvard Architecture

Unlike Von Neumann, the Harvard architecture separates memory for instructions and data, enabling simultaneous access.

Comparison

graph LR
  subgraph Harvard_Architecture
    CU[Control Unit]
    ALU[Arithmetic Logic Unit]
    IMEM["Instruction Memory"]
    DMEM["Data Memory"]
    I_O[I/O Devices]
  end

  CU --> IMEM
  CU --> DMEM
  ALU --> DMEM
  DMEM --> ALU
  CU --> I_O

Central Processing Unit (CPU)

The CPU is the brain of the computer, executing instructions through coordinated control and arithmetic operations.

Key Components

graph TB
  subgraph CPU
    CU[Control Unit]
    ALU[Arithmetic Logic Unit]
    REG[Registers]
    CLK[Clock]
  end
  CU --> ALU
  CU --> REG
  REG --> ALU
  ALU --> REG
  CU --> CLK

Instruction Cycle

The Instruction Cycle describes how the CPU processes an instruction, typically through four main stages.

Steps

1. Fetch: Retrieve the instruction from memory.
2. Decode: Interpret the opcode and operands.
3. Execute: Perform the operation via ALU or control logic.
4. Store: Write results back to memory or registers.

flowchart LR
  F[Fetch] --> D[Decode] --> E[Execute] --> S[Store] --> F

Each instruction requires multiple clock cycles, and performance depends on the efficiency of these stages.

Memory Hierarchy

Memory systems balance speed, size, and cost through a hierarchical organization.

graph TD
  R[Registers] --> C1[L1 Cache] --> C2[L2 Cache] --> M[Main Memory] --> S[Secondary Storage] --> T[Tertiary Storage]

The principle of locality (temporal and spatial) drives cache design — recently used data is likely to be reused soon.

Buses and Communication

Data flow between components is facilitated by system buses:

graph LR
  CPU -->|Address Bus| MEM
  CPU -->|Data Bus| MEM
  CPU -->|Control Bus| MEM

Machine Instructions and Assembly

Each CPU supports a specific Instruction Set Architecture (ISA) — defining valid operations and binary encodings.

Example (Simplified)

graph TD
  MEM[Memory] --> CU
  CU --> ALU
  ALU --> REG[Registers]
  REG --> MEM

Pipelining

Instruction pipelining improves CPU throughput by overlapping execution phases of multiple instructions.

gantt
    dateFormat  X
    title CPU Instruction Pipeline
    section Stages
    IF :active, 0, 1
    ID : 1, 2
    EX : 2, 3
    MEM : 3, 4
    WB : 4, 5

Each instruction enters a different pipeline stage every clock cycle, increasing parallelism.

CPU Performance Metrics

Performance can be expressed using cycles per instruction (CPI) and clock frequency.

Alternatively:

Example

A processor with 2 GHz clock and average CPI = 1.5 executing 1 billion instructions:

Cache Performance

Cache efficiency is measured via Average Memory Access Time (AMAT):

• Hit Time: Time to access data in cache.
• Miss Rate: Fraction of memory accesses not found in cache.
• Miss Penalty: Time to fetch data from main memory.

Improving cache size and associativity reduces miss rate but increases cost and power consumption.

Modern CPU Design

Modern CPUs include multiple cores, speculative execution, and branch prediction.

graph TB
  subgraph Multi-Core_CPU
    CORE1[Core 1]
    CORE2[Core 2]
    L1C[L1 Cache]
    L2C[L2 Cache]
    L3C[L3 Shared Cache]
    MEM[Main Memory]
  end

  CORE1 --> L1C
  CORE2 --> L1C
  L1C --> L2C
  L2C --> L3C
  L3C --> MEM

Branch Prediction Example

Predicts the outcome of conditional branches before execution to minimize pipeline stalls.

Summary

• The CPU coordinates instruction processing through ALU, CU, and registers.
• The Von Neumann model introduced stored-program architecture.
• Harvard architecture separates instruction and data paths for speed.
• Pipelining and cache hierarchies maximize parallelism and efficiency.
• Performance metrics such as CPI, MIPS, and AMAT quantify design trade-offs.
• Modern systems integrate multi-core, speculative, and out-of-order execution.

References

• Patterson, D. A., & Hennessy, J. L. (2021). Computer Organization and Design: The Hardware/Software Interface (6th ed.). Morgan Kaufmann.
• Stallings, W. (2019). Computer Organization and Architecture (11th ed.). Pearson.
• Tanenbaum, A. S., & Austin, T. (2013). Structured Computer Organization (6th ed.). Pearson.
• Mano, M. M., & Ciletti, M. D. (2017). Digital Design (6th ed.). Pearson.
• University of Cambridge — Computer Laboratory. Computer Architecture Course Notes.
• IEEE Computer Society. (2019). IEEE Standard for Microprocessor Systems.
• NIST. (2020). Digital System Architecture Guidelines.